
C. WeltinWu,
G. Zhao, I. Galton, "A 3.5 GHz Digital FractionalN PLL Frequency Synthesizer
Based on Ring Oscillator FrequencytoDigital Conversion," IEEE Journal of Solid State Circuits, vol. 50, no. 12, pp.
2988  3002, December 2015.


C. Venerus, I. Galton,
"Quantization Noise Cancellation for FDCBased FractionalN PLLs," IEEE
Transactions on Circuits and Systems II: Express Briefs , vol. 62, no. 12, pp. 1119 
1123, December 2015.


C. WeltinWu, E. Familier, I.
Galton, "A Linearized Model for the Design of FractionalN Digital PLLs
Based on DualMode Ring Oscillator FDCs," IEEE Transactions of
Signals and Systems I: Regular Papers, vol. 62, no. 8, pp. 2013  2023, August
2015.


C. WeltinWu, G. Zhao, I.
Galton, "A Highly Digital Frequency Synthesizer Using RingOscillator
FrequencytoDigital Conversion and Noise Cancellation," IEEE
International Solid State Circuits Conference, 2015, Digest of Technical
Papers, February 2015.


C. Venerus, I. Galton,
"A TDCFree MostlyDigital FDCPLL Frequency Synthesizer With A 2.83.5
GHz DCO," IEEE Journal of Solid State Circuits, vol. 50, no. 2,
February 2015.


C. Venerus,
"DeltaSigma FDC Based FractionalN PLLs with MultiRate Quantizing
Dynamic Element Matching," Ph.D. Dissertation, University of California,
San Diego, 2013.


E. Familier, C. Venerus, I. Galton, "A Class of Quantizers With DCFree
Quantization Noise and Optimal Immunity to NonlinearityInduced Spurious
Tones," IEEE Transactions on Signal Processing, vol. 61, no. 17,
pp. 4270  4238, September 2013.


E. Familier, I.
Galton, "A Fundamental Limitation of DCFree Quantization Noise With
Respect to NonlinearityInduced Spurious Tones," IEEE Transactions on
Signal Processing, vol. 61, no. 16, pp. 4172  4180, August 2013.


C. Venerus, I. Galton, "DeltaSigma FDC Based FractionalN PLLs," IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 60, no. 5, pp. 12741285,
May 2013.


N. Rakuljic, I. Galton, "Suppression of QuantizationInduced
Convergence Error in Pipelined ADCs With Harmonic Distortion
Correction," IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 60, no. 3, pp. 593602, March 2013.


G. Taylor, I. Galton,
"A Reconfigurable
MostlyDigital DeltaSigma ADC with a Worstcase FOM of 160dB," IEEE Journal of
SolidState Circuits, vol. 48, no. 4, pp. 983  995, February 2013.


N. Rakuljic, "A Generalized TreeStructured DEM DAC
and Enhanced Harmonic Distortion Correction in Pipelined ADCs," Ph.D.
dissertation, University of California, San Diego, 2012.


G. Taylor, I. Galton,
"A Reconfigurable
MostlyDigital DeltaSigma ADC with a Worstcase FOM of 160dB," IEEE Symposium on
VLSI Circuits, pp. 166  167, June 1315, 2012.


G. Taylor, "Mostly Digital ADCs for Highly Scaled CMOS Processes,"
Ph.D. dissertation, University
of California,
San Diego,
2011.


K. Wang, I. Galton, "A DiscreteTime Model for the Design of TypeII PLLs With
Passive Sampled Loop Filters," IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 2,
pp. 264275, February 2011.


K. Wang, "Spur Reduction Techniques for FractionalN PLLs,"
Ph.D. dissertation, University
of California,
San Diego,
2010.


I. Galton, "Why DynamicElementMatching DACs Work," IEEE
Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 2,
pp. 6974, March 2010.


N. Rakuljic, I. Galton, "TreeStructured DEM DACs with
Arbitrary Numbers of Levels," IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 57, no. 2, pp. 313322, February 2010.


G. Taylor, I. Galton,
"A MostlyDigital
VariableRate ContinuousTime DeltaSigma Modulator ADC," IEEE
Journal of SolidState Circuits, vol. 45, no. 12, pp. 2634  2646,
December 2010.


G. Taylor, I. Galton,
"A MostlyDigital
VariableRate ContinuousTime ADC DeltaSigma Modulator," IEEE
International Solid State Circuits Conference, 2010, Digest of Technical
Papers, pp. 298  299, February 2010.


A. Panigada, "Harmonic Distortion Correction in
Pipelined Analog to Digital Converters," Ph.D. dissertation, University of California, San Diego,
2009.


A. Panigada, I. Galton,
"A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital
Harmonic Distortion Correction," IEEE Journal of SolidState Circuits,
vol. 44, no. 12, pp. 3314  3328, December 2009.


Panigada, I.
Galton, "A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital
Harmonic Distortion Correction," IEEE International SolidState
Circuits Conference, 2009, Digest of Technical Papers, pp. 162163,
February 2009.


K. J. Wang, A. Swaminathan,
I. Galton, "Spurious Tone Suppression Techniques Applied to a
WideBandwidth 2.4 GHz FractionalN
PLL," IEEE Journal of SolidState Circuits, vol. 43, no. 12, pp.
2787  2797, December 2008.


K. L. Chan, N. Rakuljic, I. Galton, "Segmented Dynamic Element Matching for
HighResolution DigitaltoAnalog Conversion," IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3383  3392,
December 2008.


K. L. Chan, J. Zhu, I. Galton, "Dynamic Element Matching to Prevent Nonlinear
Distortion From PulseShape Mismatches in HighResolution DACs,"
IEEE Journal of SolidState Circuits, vol. 43, no. 9, pp. 2067  2078,
September 2008.


K. J. Wang, A. Swaminathan,
I. Galton, "SpuriousTone Suppression Techniques Applied to a
WideBandwidth 2.4GHz FractionalN
PLL," IEEE International SolidState Circuits Conference, 2008,
Digest of Technical Papers, pp. 342343, 618, February 2008.


K. L. Chan, "High Speed, High Resolution
DigitaltoAnalog Converters," Ph.D. dissertation, University of California, San Diego,
2007.


A. Swaminathan, K. J. Wang,
I. Galton, "A WideBandwidth 2.4 GHz ISM Band FractionalN PLL With Adaptive Phase Noise
Cancellation," IEEE Journal of SolidState Circuits, vol. 42, no.
12, pp. 2639  2650, December 2007.


A. Swaminathan, A. Panigada, E. Masry, I. Galton,
"A Digital Requantizer With Shaped Requantization Noise That Remains
Well Behaved After Nonlinear Distortion," IEEE Transactions on Signal
Processing, vol. 55, no. 11, pp. 5382  5394, November 2007.


K. L. Chan, J. Zhu, I. Galton, "A 150MS/s 14bit
Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquist
Band," IEEE Symposium on VLSI Circuits, pp. 200  201, June 14,
2007.


S. Pamarti, I. Galton, "LSB Dithering in MASH DeltaSigma D/A
Converters," IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 54, no. 4, pp. 779  790, April 2007.


S. Pamarti, J. Welz, I. Galton,
"Statistics of the Quantization Noise in 1Bit Dithered SingleQuantizer
Digital DeltaSigma Modulators," IEEE Transactions on Circuits and
Systems I: Regular Papers, vol. 54, no. 3, pp. 492  503, March 2007.


A. Swaminathan, K. Wang, I. Galton, "A WideBandwidth 2.4GHz ISMBand
FractionalN PLL with Adaptive
PhaseNoise Cancellation," IEEE International SolidState Circuits
Conference, 2007. Digest of Technical Papers, pp. 302  604, February
2007.


A. Swaminathan, "Enabling Techniques for Low
Power, High Performance FractionalN
Frequency
Synthesizers," Ph.D. dissertation, University of California, San Diego,
2006.


A. Panigada, I. Galton, "Digital Background Correction of
Harmonic Distortion in Pipelined ADCs," IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. 53, no. 9, pp. 1885  1895, September
2006.


J. Rode, A. Swaminathan, I. Galton, P. M. Asbeck,
"FractionalN Direct Digital
Frequency Synthesis with a 1Bit Output," IEEE MTTS International
Microwave Symposium Digest, pp. 415  418, June 2006.


K. L. Chan, I.
Galton, "A 14b 100MS/s DAC with Fully Segmented Dynamic Element
Matching," IEEE International SolidState Circuits Conference, 2006.
Digest of Technical Papers, pp. 2390  2399, February 2006.


J.L. Ceballos, I. Galton, G.C. Temes,
"Stochastic AnalogtoDigital Conversion," 48th Midwest Symposium on Circuits and Systems, 2005,
pp. 855  858, August 2005.


S. Pamarti, L. Jansson, I. Galton,
"Addition to "A Wideband 2.4GHz DeltaSigma FractionalN PLL With 1Mb/s InLoop
Modulation,"" IEEE Journal of SolidState Circuits, vol. 40,
no. 2, pp. 559  559, February 2005.


M. Y. Li, I. Galton,
L. E. Larson, P. M. Asbeck, "Nonlinearity
Estimation and Spectral Regrowth Prediction of Power Amplifiers Using
Correlation Techniques," The 2005 IEEE Annual Conference Wireless and
Microwave Technology, pp. 170  173, 2005.


E. Siragusa,
I. Galton, "A Digitally Enhanced 1.8V 15bit 40MSample/s CMOS
Pipelined ADC," IEEE Journal of SolidState Circuits, vol. 39,
no. 12, pp. 2126  2138, December 2004.


M. Y. Li, I. Galton,
L. E. Larson, P. M. Asbeck, "Correlation
Techniques for Estimation of Amplifier Nonlinearity," 2004 IEEE Radio
and Wireless Conference, pp. 179  182, September 2004.


S. Ye, I.
Galton, "Techniques for Phase Noise Suppression in Recirculating
DLLs," IEEE Journal of SolidState Circuits, vol. 39, no. 8, pp.
1222  1230, August 2004.


J. Welz, I. Galton, "A
Tight SignalBand Power Bound on Mismatch Noise in a MismatchShaping
DigitaltoAnalog Converter," IEEE Transactions on Information Theory,
vol. 50, no. 4, pp. 593  607, April 2004.


S. Pamarti, L. Jansson, I. Galton, "A Wideband 2.4GHz DeltaSigma
FractionalN PLL with 1Mb/s
InLoop Modulation," IEEE Journal of SolidState Circuits, vol.
39, no. 1, pp. 49  62, January 2004.


E. Siragusa, I. Galton, "A Digitally Enhanced 1.8 V 15 b 40
MS/s CMOS Pipelined ADC," IEEE International SolidState Circuits
Conference, 2004. Digest of Technical Papers, pp. 452  538, February
2004.


S. Pamarti, "Enabling
Techniques for Wide Bandwidth FractionalN PhaseLocked Loops,"
Ph.D. dissertation, University
of California,
San Diego,
2003.


S. Ye, "Phase
Realignment and Phase Noise Suppression in PLLs and DLLs," Ph.D.
dissertation, University
of California,
San Diego,
2003.


E. Siragusa, "Digitally
Enhanced High Resolution Pipelined AnalogtoDigital Conversion," Ph.D.
dissertation, University
of California,
San Diego,
2003.


S. Pamarti, I. Galton, "PhaseNoise Cancellation Design
Tradeoffs in DeltaSigma FractionalN
PLLs," IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 50, no. 11, pp. 829  838, November 2003.


S. Ye, L. Jansson,I. Galton,
"Techniques for InBand Phase Noise Suppression in Recirculating
DLLs," Proceedings of the IEEE 2003 Custom Integrated Circuits
Conference, pp. 297  300, September 2003.


J. Welz, "The Analysis
and Design of Mismatch Shaping DigitaltoAnalog Converters," Ph.D.
dissertation, University
of California,
San Diego,
2002.


S. Ye, L. Jansson, I.
Galton, "A MultipleCrystal Interface PLL with VCO Realignment to Reduce
Phase Noise," IEEE Journal of SolidState Circuits, vol. 37, no.
12, pp. 1795  1803, December 2002.


J. Welz, I. Galton,
"Necessary and Sufficient Conditions for Mismatch Shaping in a General
Class of Multibit DACs," IEEE Transactions on Circuits and Systems
II: Analog and Digital Signal Processing, vol. 49, no. 12, pp. 748759,
December 2002.


J. Keyzer, R. Uang, Y. Sugiyama, M. Iwamoto, I. Galton, P. M. Asbeck, "Generation of RF Pulsewidth
Modulated Microwave Signals Using DeltaSigma Modulation," Microwave
Symposium Digest, 2002 IEEE MTTS International, vol. 1, June 2002.


A. Fishov, E. Siragusa, J. Welz, E. Fogleman, I. Galton, "Segmented MismatchShaping D/A
Conversion," IEEE International Symposium on Circuits and Systems,
2002, pp. IV679  IV682, May 2002.


J. Welz, I. Galton, "A
Necessary and Sufficient Condition for Mismatch Shaping in MultiBit
DACs," Proceedings of the IEEE International Symposium on Circuits
and Systems, 2002, pp. I105  I108, May 2002.


P. Asbeck, I.
Galton, K.C. Wang, J. F. Jensen, A. K. Oki, C. T. M. Chang, "Digital
Signal ProcessingUp to Microwave Frequencies," IEEE Transactions on
Microwave Theory and Techniques, vol. 50, no. 3, pp. 900909, March 2002,
invited paper.


J. Grilo, I. Galton, K.
Wang, R. Montemayor, "A 12 mW
ADC DeltaSigma Modulator with 80dB of Dynamic Range Integrated in a
SingleChip Bluetooth Transceiver," IEEE Journal of SolidState
Circuits, vol. 37, no. 3, pp. 271  278, March 2002.


S. Ye, L. Jansson, I. Galton, "A MultipleCrystal Interface PLL with
VCO Realignment to Reduce Phase Noise," IEEE International
SolidState Circuits Conference, 2002. Digest of Technical Papers, pp. 7879,
446, February 2002.


G. Chang, L. Jansson, K.
Wang, J. Grilo, R. Montemayor,
C. Hull, M. Lane, A. X. Estrada, M. Anderson, I. Galton, S. V. Kishore,
"A DirectConversion SingleChip RadioModem for Bluetooth," IEEE
International SolidState Circuits Conference, pp. 8889, 448, February
2002.


I. Galton, "DeltaSigma Data Conversion in
Wireless Transceivers," IEEE Transactions on Microwave Theory and
Techniques, vol. 50, no. 1, pp. 302316, January 2002, invited paper.


J. Welz, I.
Galton, E. Fogleman, "Simplified Logic for
FirstOrder and SecondOrder MismatchShaping DigitaltoAnalog
Converters," IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 48, no. 11, pp. 10141028, November 2001.


P. M. Asbeck, L. E. Larson,
I. Galton, "Synergistic Design of DSP and Power Amplifiers for Wireless
Communications," IEEE Transactions on Microwave Theory and Techniques,
vol. 49, no. 11, pp. 21632169, November 2001.


J. Grilo, I. Galton, K.
Wang, R. Montemayor, "A 12 mW
ADC DeltaSigma Modulator with 80dB of Dynamic Range Integrated in A
SingleChip Bluetooth Transceiver," IEEE Custom Integrated Circuits
Conference, 2001, pp. 2326, May 2001.


J. Welz, I.
Galton, "The MismatchNoise PSD from a TreeStructured DAC in a
SecondOrder DS Modulator with a Midscale Input," Proc. of the IEEE
International Conference on Acoustics, Speech, and Signal Processing,
vol. 4, pp. 26252628, May 2001.


J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, P. Asbeck, "Digital Generation of RF Signals for
Wireless Communications with BandPass DeltaSigma Modulation," IEEE
MTTS International Microwave Symposium Digest, pp. 21272130, May 2001.


E. Fogleman, J. Welz, I. Galton, "An Audio ADC DeltaSigma Modulator
with 100dB Peak SINAD and 102dB DR Using a SecondOrder MismatchShaping
DAC," IEEE Journal of SolidState Circuits, vol. 36, no. 3, pp.
339348, March 2001.


E. Fogleman, I. Galton, "A Digital CommonMode Rejection
Technique for Differential AnalogtoDigital Conversion," IEEE
Transactions on Circuits and Systems II: Analog and Digital Signal Processing,
vol. 48, no. 3, pp. 255  271, March 2001.


E. Fogleman, I. Galton, "A Dynamic Element Matching Technique
for ReducedDistortion Multibit Quantization in DeltaSigma ADCs," IEEE
Transactions on Circuits and Systems II: Analog and Digital Signal Processing,
vol. 48, no. 2, pp. 158170, February 2001.


E. Fogleman, "Enabling
Techniques for HighResolution AnalogtoDigital Conversion in IC Fabrication
Processes Optimized for Digital Circuits," Ph.D. dissertation, University of California, San Diego,
2000.


E. Fogleman, J. Welz, I. Galton, "An Audio ADC DeltaSigma Modulator
with 100 dB Peak SINAD and 102 dB DR Using a SecondOrder MismatchShaping
DAC," Proceedings of the IEEE 2000 Custom Integrated Circuits
Conference, pp. 17  20, May 2000.


E. J. Siragusa, I Galton,
"Gain Error Correction Technique for Pipelined Analoguetodigital
converters," IEE Electronics Letters, vol. 36, no. 7, pp.
617618, March 30, 2000.


I. Galton, "Digital Cancellation of D/A Converter
Noise in Pipelined A/D Converters," IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing, vol. 47, no. 3, pp.
185196, March 2000.


E. Fogleman, I. Galton, W.
Huff, H. T. Jensen, "A 3.3V SinglePoly CMOS Audio ADC DeltaSigma
Modulator with 98dB Peak SINAD and 105dB Peak SFDR," IEEE Journal of
Solid State Circuits, vol. 35, no. 3, pp. 297307, March 2000.


E. Fogleman, I. Galton, H.T. Jensen, "A Dynamic Element
Matching Technique for ReducedDistortion Multibit Quantization in
DeltaSigma ADCs," Proceeding of the IEEE International Symposium on
Circuits and Systems, pp. 290  293, June 1999.


E. Fogleman, I. Galton, H.T. Jensen, "An AreaEfficient
Differential Input ADC with Digital Common Mode Rejection," Proceedings
of the IEEE International Symposium on Circuits and Systems, pp. 347 
350, June 1999.


E. Fogleman, I. Galton, W.
Huff, H.T. Jensen, "A 3.3V SinglePoly CMOS Audio ADC DeltaSigma
Modulator with 98 dB Peak SINAD," Proceedings of the IEEE 1999 Custom
Integrated Circuits Conference, pp. 121  124, May 1999.


I. Galton, W. Huff, P. Carbone, E. Siragusa,
"A DeltaSigma PLL for 14b 50kSample/s FrequencytoDigital Conversion
of a 10 MHz FM Signal," IEEE Journal of Solid State Circuits,
vol. 33, no. 12, pp. 20422053, December 1998.


H.T. Jensen and I.
Galton, "An Analysis of the Partial Randomization Dynamic Element
Matching Technique," IEEE Transactions on Circuits and Systems II:
Analog and Digital Signal Processing, vol. 45, no. 12, pp. 15381549,
December 1998.


H.T. Jensen, I.
Galton, "A ReducedComplexity MismatchShaping DAC for DeltaSigma Data
Converters," Proceedings of IEEE Symposium on Circuits and Systems,
1998, vol. 1, pp. 504507, May 1998.


W. Huff, I. Galton,
"NonuniformtoUniform Decimation for
DeltaSigma FrequencytoDigital Conversion," Proceedings of IEEE
Symposium on Circuits and Systems, 1998, vol. 1, pp. 365368, May 1998.


I. Galton, W. Huff, P. Carbone, E. Siragusa,
"A DeltaSigma PLL for 14b 50kSample/s FrequencytoDigital Conversion
of a 10 MHz FM Signal," IEEE International SolidState Circuits
Conference, 1998. Digest of Technical Papers, vol. 41, pp. 366367,
February 1998.


H.T. Jensen and I.
Galton, "A LowComplexity Dynamic Element Matching DAC for Direct
Digital Synthesis," IEEE Transactions on Circuits and Systems II:
Analog and Digital Signal Processing, vol. 45, no. 1, pp. 1327, January
1998.


E.T. King, A. Eshraghi, I.
Galton, T.S. Fiez, "A NyquistRate DeltaSigma
A/D Converter," IEEE Journal of Solid State Circuits, vol. 33,
no. 1, pp. 4552, January 1998.


H.T. Jensen, "Analyses of Dynamic Element
Matching Techniques for Data Conversion," University of California, San Diego,
1997.


I. Galton, "Spectral Shaping of Circuit Errors in
DigitaltoAnalog Converters," IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing, vol. 44, no. 10, pp.
808817, November 1997.


H.T. Jensen, I.
Galton, "A Performance Analysis of the Partial Randomization Dynamic
Element Matching DAC Architecture," Proceedings of the IEEE
International Symposium on Circuits and Systems, 1997, vol. 1, pp. 912,
June 1997.


H.T. Jensen, I.
Galton, "Yield Estimation of a FirstOrder NoiseShaping D/A
Converter," Proceedings of the IEEE International Symposium on
Circuits and Systems, 1997, vol. 1, pp. 441444, June 1997.


I. Galton and H.T. Jensen, "Oversampling Parallel
DeltaSigma Modulator A/D Conversion," IEEE Transactions on Circuits
and Systems II: Analog and Digital Signal Processing, vol. 43, no. 12,
pp. 801810, May 1996.


I. Galton, "NoiseShaping D/A Converters for
DeltaSigma Modulation," Proceedings of the 1998 International
Symposium on Circuits and Systems, 1996, vol. 1, pp. 441  444, May 1996.


I. Galton, H.T. Jensen, J.J. Rosenberg, D.A. Towne,
"Clock Distribution Using Coupled Oscillators," Proc. of the
IEEE International Symposium on Circuits and Systems, vol. 3, pp.
217220, May 1996.


H.T. Jensen, I.
Galton, "A HardwareEfficient DAC for Direct Digital Synthesis," Proc.
of the IEEE International Symposium on Circuits and Systems, vol. 4, pp.
97100, May 1996.


I. Galton and H.T. Jensen, "DeltaSigma Modulator
Based A/D Conversion Without Oversampling," IEEE Transactions on
Circuits and Systems II: Analog to Digital Signal Processing, vol. 42,
no. 12, pp. 773784, December 1995.


I. Galton and P. Carbone, "A Rigorous Analysis of
D/A Conversion with Dynamic Element Matching," IEEE Transactions on
Circuits and Systems II: Analog and Digital Signal Processing, vol. 42,
no. 12, pp. 763772, December 1995.


I. Galton, "AnalogInput Digital PhaseLocked
Loops for Precise Frequency and Phase Demodulation," IEEE
Transactions on Circuits and Systems II: Analog and Digital Processing,
vol. 42, no. 10, pp. 621630, November 1995.


H.T. Jensen, I.
Galton, "A Robust Parallel DeltaSigma A/D Converter Architecture,"
Proceedings of the IEEE International Symposium on Circuits and Systems,
1995, vol. 2, pp. 13401343, May 1995.


I. Galton, "A Practical SecondOrder DeltaSigma
FrequencytoDigital Converter," Proceedings of the IEEE
International Symposium on Circuits and Systems, 1995, vol. 1, pp. 58,
May 1995.


E. King, F. Aram, T. Fiez,
I. Galton, "Parallel DeltaSigma A/D Conversion," Proceedings of
the IEEE Custom Integrated Circuits Conference, 1994, pp. 503506, May
1994.


I. Galton, "HigherOrder DeltaSigma
FrequencytoDigital Conversion," Proceedings of the IEEE
International Symposium on Circuits and Systems, 1994, vol. 5, pp.
441444, May 1994.


P. Carbone, I. Galton, "Conversion Error in D/A
Employing Dynamic Element Matching," Proceedings of the IEEE
International Symposium on Circuits and Systems, 1994, vol. 2, pp. 1316,
May 1994.


I. Galton, "Granular Quantization Noise in a
Class of DeltaSigma Modulators," IEEE Transactions on Information
Theory, vol. 40, no. 3, pp. 848859, May 1994.


I. Galton, "Granular Quantization Noise in the
FirstOrder DeltaSigma Modulator," IEEE Transactions on Information
Theory, vol. 39, no. 6, pp. 19441956, November 1993.


I. Galton, G. Zimmerman, "Combined RF Phase
Extraction and Digitization," Proceedings of the IEEE International
Symposium on Circuits and Systems, 1993, vol. 2, pp. 1104  1107, May
1993.


I. Galton, "OneBit Dithering in DeltaSigma
ModulatorBased D/A Conversion," Proc. of the IEEE International
Symposium on Circuits and Systems, 1993, vol. 2, pp. 1310  1313, May
1993.


I. Galton, "An Efficient Three Point Arc
Algorithm," IEEE Computer Graphics and Applications, vol. 9, no.
6, pp. 4449, 1989.
